1. Field of the Invention
The present invention generally relates to a semiconductor memory device, and more specifically, to a semiconductor memory device having storage elements each provided with a capacitor element having three-dimensional structure and capable of accumulating more electric charges.
2. Description of the Background Art
In recent years, to apply the technique of microelectronics to industrial machinery and home appliances, a VLSI (Very-Large-Scale Integration) circuit which is a further integrated LSI (Large Scale Integration) is developed and commercially available. In the case of a semiconductor memory device, especially, the storage capacity has been increased thousand-fold in these ten years. The development of such high integration is realized by miniaturization of the size of a unit storage element, which constitutes a semiconductor memory device, by using a method called a proportional scaling.
FIG. 1 is a block diagram showing an example of a dynamic random access memory (DRAM) for storing information used in a VLSI. In the case of a DRAM one can access the desired information in a fixed access time regardless of its stored address.
Referring to FIG. 1, the DRAM includes: a memory cell array 1000 including a plurality of memory cells constituting a storage section; a row decoder 2000 and a column decoder 3000 connected respectively to a row address buffer 2100 and to a column address buffer 3100 for selecting the address of the DRAM; a control circuit 4000 for controlling the operation of the DRAM; and an input/output interface including sense amplifiers 1100 connected to an input/output circuit. A plurality of memory cells, which constitute the storage section, are disposed in a matrix form having a plurality of rows and columns. Each memory cell is connected to a corresponding word line connected to the row decoder 2000, and to a corresponding bit line connected to the column decoder 3000, to constitute a memory cell array 1000.
In response to the externally applied row address signal and column address signal, a word line and a bit line are selected respectively with the row decoder 2000 and the column decoder 3000. A memory cell is selected with the selected word line and bit line. The externally applied data are stored by the selected memory cell. The data stored in the memory cell are read out in the same manner. The read/write instruction of the data is controlled by a read/write control signal given to the control circuit 4000.
Assuming that the memory cell array 1000 has n word lines and m bit lines, the memory cell array 1000 can store N (=n.times.m) bit data. The address of the memory cell, to which the data are to be written or from which the data are read out, is retained in the row address buffer 2100 and the column address buffer 3100.
M bits of the memory cells are connected to the sense amplifiers through bit lines by the selection of a specific word line by the row decoder 2000 (selection of one word line out of n word lines). One sense amplifier out of the connected sense amplifiers is connected to the input/output circuit by the following selection of a specified bit line by the column decoder 3000 (selection of one bit line out of m bit lines). Readout or writing is operated in the memory cell connected to the input/output circuit following the instruction from the control circuit 4000.
FIG. 2 shows an equivalent circuit of a unit storage element, or a memory cell, of a DRAM. Referring to FIG. 2, a memory cell MC includes a transistor QM which works as a switching means, having a gate connected to a word line WL and one terminal connected to a bit line; and a capacitor C.sub.S for storing signals having one electrode connected to the other terminal of the transistor QM and the other electrode fixed to a potential V.sub.CP.
The writing operation of the data to the memory cell MC is performed as follows. The word line WL is activated and the transistor QM turns ON. A high level or low level potential corresponding to the information to be written is supplied to the bit line BL. An electric charge corresponding to the potential of the bit line BL is stored in the capacitor C.sub.S ; the word line WL is inactivated and the transistor QM is made OFF. The stored charges remain in the capacitor C.sub.S.
The readout of data is performed as described in the following. One electrode of the capacitor C.sub.S is fixed to a potential V.sub.CP as described above. The bit line BL is kept in a floating condition, electrically isolated from other circuits. When the word line WL is activated, the transistor QM turns ON. The charges stored in the capacitor C.sub.S are given to the bit line BL. The bit line BL has a stray capacitance of about 10 times that of the capacitor C.sub.S and so only a potential change of a few hundred mV is produced in the bit line BL in accordance with the ratio of the capacitance of the capacitor and of the bit line BL. The produced potential change is amplified by the sense amplifier 1100 to be a readout signal.
As mentioned above, the information charges stored in the capacitor C.sub.S are redistributed in the bit line BL in the reading operation to produce the potential change to be detected. The capacitance of the capacitor C.sub.S increases or decreases in proportion to the electrode surface area of the capacitor C.sub.S. Consequently, if the size of a capacitor is decreased in the higher integration, the signal charge quantity to be stored is decreased and the potential change is also made smaller, and the possibility of a misread occurs. The soft-error immunity of a memory cell is also lowered with the decrease of the signal charge quantity. In order to prevent this, it becomes necessary to use a capacitor of a specific structure to ensure the capacitance of the capacitor even if the size of it is smaller.
A two-dimensional capacitor called a planar type capacitor is mainly used for a conventional DRAM with the storage capacity less than 1M (mega=million) bits. Referring to FIG. 3, a memory cell using a conventional planar type capacitor includes a transistor 21 provided on a P-type semiconductor substrate 1, and a cell plate 3 adjacent to the transistor 21 opposing to the main surface of the P-type semiconductor substrate 1 with a dielectric film 7 interposed therebetween.
The transistor 21 includes two N.sup.+ impurity regions 14 formed with a space interposed therebetween on the P-type semiconductor substrate 1, and a gate electrode 26 formed on the region between the two N.sup.+ impurity regions 14 with a gate insulating film between the substrate 1 and the same. The gate electrode 26 is connected to the word line WL. The impurity region 14 that is not adjacent to the 10 cell plate 3 is connected to the bit line BL.
When the word line WL is activated, the transistor 21 turns ON. The potential of the two N.sup.+ impurity regions 14 substantially equals to that of the bit line BL. The cell plate 3 is connected to a fixed potential V.sub.CP, thereby electric charges are stored in the part of the main surface of the P-type semiconductor substrate 1 opposed to the cell plate 3.
In the case of a DRAM having a memory cell using a planar type capacitor, electric charges are stored on the main surface of the P-type semiconductor substrate 1, so that a large amount of area is required on the main surface. This type of a memory cell is therefore not suited to high degree of integration. For a DRAM of high degree of integration such as with more than 4M bits of capacity, a three-dimensional capacitor called a stacked type or a trench type has been introduced. FIGS. 4 and 5 show the cross-sectional structures of these types of capacitors.
Referring to FIG. 4, a memory cell with a stacked capacitor includes a transistor 21 formed on the P-type semiconductor substrate 1 and a stacked capacitor 8 adjacent to the transistor 21 on the P-type semiconductor substrate 1. The transistor 21 has the similar structure to that of the transistor 21 shown in FIG. 3. The stacked capacitor 8 includes a storage electrode 4 electrically connected to the N.sup.+ impurity region 14 which is not connected to the bit line BL, and a cell plate 3 stacked on the storage electrode 4 with a dielectric film 7 formed therebetween. The storage electrode 4 and the cell plate 3 are formed partly on the transistor 21, thereby the effective area of the charge storing portion of the stacked capacitor 8 is extended.
A memory cell with a trench type capacitor is described in the following referring to FIG. 5. The memory cell includes a transistor 21 provided on the P-type semiconductor substrate 1 and a trench type capacitor 9 provided adjacently to the transistor 21. The trench type capacitor 9 includes a dielectric film 7 formed on the sidewall of a groove 5 formed on the P-type semiconductor substrate 1, and a cell plate 3 formed on the dielectric film 7. The transistor 21 has the similar structure to that of the transistor 21 shown in FIG. 3 or FIG. 4. In the case of a trench type capacitor 9, electric charges are stored on the sidewall 6 and/or the bottom of a groove 5, so that the effective area of a storage electrode is extended. It is applicable to all other type of trench type capacitors.
As described above, it has been made possible to obtain a larger capacity with the similar-sized memory cell. However, to realize a semiconductor device of higher degree of integration such as a VLSI circuit having the capacity of 64M bits, the capacitor of such a simple three-dimensional structure turns out to be insufficient.
A solution for improving the capacitance of a capacitor is proposed in a Japanese Patent Laying-Open No. 63-313854. Referring to FIG. 6, the proposed memory cell of a DRAM includes a transistor 21 formed on a P-type semiconductor substrate 1, a storage electrode 16 having multilayered structure constituted with electrode layers of a plurality of kinds of sizes, formed adjacently to the transistor 21 on the P-type semiconductor substrate 1, a dielectric film, not shown, formed on the surface and along the circumference of the storage electrode 16, and a cell plate, not shown either, formed on the dielectric film.
Since the storage electrode 16 have multilayered structure constituted with the electrode layers having different sizes, grooves are formed on the side of the storage electrode 16 substantially parallel to the main surface of the P-type semiconductor substrate 1. The effective area of the storage electrode 16 is extended by the grooves and more electric charges can be stored therein.
The storage electrode 16 includes an undoped polysilicon film 16A provided on the N.sup.+ impurity region of a transistor 21, which is not connected to the bit line BL, and an N.sup.+ polysilicon film 16B having smaller area than the undoped polysilicon film 16A and formed on the undoped polysilicon film 16A. A unit element is constituted with an undoped polysilicon film 16A and an N.sup.+ polysilicon film 16B. The unit elements are piled up to form grooves 16C on the side of the storage electrode 16 and the effective area of the storage electrode 16 is expanded. Theoretically, the capacitance can be increased limitlessly by piling up unit elements. But this method is not practical. A certain steps of manufacturing are required. Imperfections included in the layers induces a lower yield, and more complicated process. The number of layers, therefore, is limited.
There is another example proposed by Wakamiya et al. in "Novel Stacked Capacitor Cell for 64-Mb DRAM" (1989 Symposium on VLSI Technology Digest of Technical Papers, pp. 69-70). In the paper, a cylindrical capacitor is proposed. FIG. 7 shows a perspective view of the proposed memory cell. FIG. 8 is a plan view of the adjacent two of the proposed memory cells. FIG. 9 is a cross-sectional view taken in the direction of the arrows along the line IX--IX in FIG. 8.
A memory cell of a DRAM using a cylindrical capacitor proposed by Wakamiya et al. will be described referring to FIGS. 7 to 9 in the following. The memory cell includes: a P-type semiconductor substrate 1, a field-isolation oxide film 23 constituted with a thick oxide film formed on the P-type semiconductor substrate 1 for separating memory cells from each other; a transistor 21 with a gate electrode 26 of the first word line provided where there is no field-isolation oxide film 23; and a hollow cylindrical capacitor 10 connected the transistor 21 and formed on the transistor 21 and the field-isolation oxide film 23. An insulating film 34 is formed on the P-type semiconductor substrate 1 and on the field-isolation oxide film 23. On the part of the insulating film 34 formed on the field-isolation oxide film 23, a second word line 27 is disposed for driving other memory cells provided along the direction of a word line.
The transistor 21 includes two N.sup.+ impurity regions 24 formed with a space therebetween on the semiconductor substrate 1 and a gate electrode 26 formed on the main surface of the P-type semiconductor substrate 1 between the two N.sup.+ impurity regions 24 with a dielectric film 25 formed therebetween. The insulating film 34 is formed on the gate electrode 26 upon which a nitride film 35 for masking is formed.
The cylindrical capacitor includes: a lower electrode 28 constituted with polysilicon layers bordering on an N.sup.+ impurity region 24 and formed over the insulating film 34 and the nitride film 35; a hollow cylindrical electrode 28a constituted with polysilicon and integrally formed on the lower electrode 28; a dielectric film 29 (not shown in FIG. 7) formed on the cylindrical electrode 28a; and a conductive layer 30 (not shown in FIG. 7) formed on the dielectric film 29.
Referring particularly to FIG. 9, an interlayer insulating film 40 is formed in the memory cell. A bit line 42 is formed with tungsten silicide film, etc. on the interlayer insulating film 40. On an N.sup.+ impurity region 24, to which the cylindrical capacitor 10 is not connected, a contact hole 41 is formed in the insulating film 40. A tungsten silicide film 43 is formed inside the contact hole 41. The bit line 42 is electrically connected to an N.sup.30 impurity region 24 with the tungsten silicide film 43.
In a memory cell having the constitution as mentioned above, when a word line (a gate electrode) 26 is activated, the transistor 21 turns ON. The bit line 42 is electrically connected to the lower electrode 28 and the cylindrical electrode 28a. When data are to be written, the charges corresponding to the potential of the bit line 42 are stored in the lower electrode 28 and the cylindrical electrode 28a. When data are readout, the charges stored in the lower electrode 28 and the cylindrical electrode 28a are given to the bit line 42.
In a memory cell using a proposed cylindrical capacitor, the storage capacitance can be increased by making the cylindrical electrode 28a higher. Electric charges are stored not only on the outer-peripheral surface but also on the inner-peripheral surface of the cylindrical electrode 28a, so that the capacitance is effectively increased with the height of the cylindrical electrode 28a.
Among the examples described above, the last two make it possible to realize higher degree of integration of a semiconductor memory device. For the realization of a semiconductor memory device, however, with more than 256-Mb storage capacity for example, there are problems still to be solved.
In a stacked capacitor with multilayered structure as shown in FIG. 6, to increase the storage capacitance, it is necessary to form a plurality of layers constituted with an undoped polysilicon film 16A and an N.sup.+ polysilicon film 16B. The fabricating procedure of the capacitors of this type includes may steps; therefore it is not economical to manufacture this kind of capacitors. In addition, it is difficult to fabricate this type of capacitors having high reliability.
The cylindrical capacitor shown in FIGS. 7 to 9 has merit in that the hollow cylindrical electrode can be formed with only one patterning. To realize a DRAM with a storage capacity of more than 256-Mb, however, it is necessary to make the diameter of a hollow cylindrical electrode 28a smaller. Since it is difficult to make the cylindrical electrode 28a very high, it cannot be avoided to decrease the capacitance of a memory cell. Consequently, it is difficult to fabricate a DRAM of higher degree of integration or to realize the operation of high reliability using the memory cells of this type.